In modern digital communications systems, the receiver must have a clock and data recovery ("CDR") system to decode and decipher data. Two standards for data transmission at bit rates ranging from 100s of MB/sec to more than 1 GB/sec make particular demands on the CDR system. These standards are SONET/SDH at 155 and 622 MB/sec and Fibre-Channel at 531.25 and 1062.5 MB/sec.
Earlier CDR systems have been implemented with surface acoustic wave("SAW") technology, which is difficult to use in integrated circuits("IC"s) and the resultant CDRs are therefore expensive. Recently, phase lock loop("PLL") designs have substantially reduced the cost of CDR systems. All PLL systems have a phase detector, some type of loop filter, and a voltage controlled oscillator("VCO").
For SONET/SDH data transmission environments, strict specifications are imposed on the CDR system in terms of jitter performance, including specified levels of jitter transfer, jitter tolerance, and jitter generation. These terms are defined in The International Telegraph and Telephone Consultative Committee Recommendation G.958, "Digital Line Systems Based On The Synchronous Digital Hierarchy For Use On Optical Fibre Cables", incorporated herein for all purposes. With jitter transfer and jitter tolerance, the corner frequencies of phase modulation at the input of the CDR system are defined, and are directly related to the behavior of the PLL.
One known PLL architecture that has been successful in CDR systems operating at bit rates exceeding 1 GB/sec uses a special VCO. This architecture combines part of the loop filter function with the VCO by feeding the phase detector output directly into a "bang/bang" input of the VCO. A dual input VCO is therefore required. The first input is the commonly known analog voltage input, upon which analog voltage the VCO output frequency is monotonically dependent. The second input is a digital signal input. Depending upon a logic high or logic low signal, the VCO's output frequency alternates between two small but distinct "bang/bang"frequencies. This architecture stabilizes the overall PLL, provided that the phase change due to the bang/bang frequency loop is larger than the phase change introduced by the loop filter.
In one known dual input VCO CDR system, the VCO is realized as a ring oscillator consisting of three variable delay cells and a bang/bang modulation delay cell. The variable delay cell interpolates between two paths, each path having a different delay. The bang/bang delay is achieved by modulating the bias current of an inverting gain stage biased below the peak f.sub.T current.
This first known design has been improved by embedding the bang/bang control within the variable delay cell, which provides the VCO with a larger frequency range.
In both known designs, the bang/bang delay is dependent on the inherent delays of inverters. This makes the bang/bang frequency sensitive to the process, temperature, and supply voltage variations inherent in the fabrication and operation of inverters. In known application, the bang/bang frequency is simply designed large enough to provide loop stability with ample margin.
Unfortunately, these two approaches do not give enough control over the bang/bang frequency to comply with strict SONET/SDH jitter requirements. The dual loop PLL CDR system can be adapted to meet the SONET/SDH jitter requirements provided that the bang/bang frequency of the VCO can be set with precision and then remain constant over temperature and supply voltage variations. The bang/bang frequency directly determines the jitter transfer and jitter tolerance corner frequencies and must be set to meet the corresponding SONET/SDH requirements.